Generators for true random numbers based on electronic noise (“True Random Number Generators”) are an important part of (multi-) processor systems, e.g. for applications in cryptography and scientific computing.
For the use in cryptography and scientific calculations a technical goal is the efficient generation of truly random numbers that are truly random and not pseudorandom. Because a private or secret parameter which is generated by a true random number generator is an interesting property to an attacker. Therefore, the generation of a random bit sequence is important and should be unpredictable to an attacker. One common method for generating a truly random sequence is to amplify the thermal noise in a diode. The disadvantage of this method is the use of external components. This approach enables an attacker to manipulate and read the random bit sequence from the device and consequently violate the security of the entire cryptographic system.
Therefore and in general, true random number generators are implemented as a separate circuit block, which e.g. is used as a central component in a system-on-chip. In U.S. Pat. No. 8,131,789 B2 a true random number generation circuitry is disclosed, whereas the circuitry utilizes a pair of oscillators driving a pair of linear feedback shift registers (LFSR) with their outputs being combined to generate random numbers. At least one of the oscillators is programmable with variable frequency, whereas at least two independent variable frequency ring oscillators whose outputs feed the independent linear feedback shift registers are necessary. So, U.S. Pat. No. 8,131,789 B2 uses dedicated, free running, ring oscillators only for random number generation. It uses the clock output signal. The drawback is additional power consumption and chip area (or FPGA resources). The disadvantage is the amount of chip area that is needed for realizing this circuitry for generating the true random numbers.
In K. Wold, et al: “Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings”, Int. Conference of Reconfigurable Computing and FPGAs, 385-390, doi:10.1109/ReConFig.2008.17, 2008 a true random number generator is constructed from many equal length oscillators whereas the clock outputs of several of these oscillators are linked via an XOR network in order to increase the entropy. It also proposes to add an extra flip-flop for sampling of the ring oscillator output clock. This will not be required in this invention, since the phase frequency detector (PFD) signal of the phase locked loops (PLL) is used as random source. The entropy is an important parameter in generating true random numbers, because it is a measurement for the amount of information included in the signal. This means, if the stream is for some reason predictable (e.g. significant correlations in the bits of the stream) and therefore not random, the information in this stream is low. Hence good randomness goes along with high entropy i.e. information.
Another approach for generating true random numbers is the usage of clock output signals of phase locked loops (PLL). In Drutarovsky, et al.: “Cyptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator”,Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on, vol., no., pp.1,6, 16-18 Apr. 2008 the basic principle behind the true random number generation is to extract the randomness from the jitter of the clock signals synthesized in the embedded analog PLLs, whereas the intrinsic part of jitter generated mainly in an analog Voltage Controlled Oscillator (VCOs) of PLLs. But for this solution, defined frequency ratios of the PLLs must be presented or active measures must be taken to synchronize the clock generators (PLLs). So the proposed true random generation uses the clock output signals of two different PLLs (here on FPGA) and combine them for random number generation by sampling with multiple flip-flops. This requires the resources (area and power) of two PLLs and demands for additional synchronization effort to generate good random data streams. The design is sensitive to mismatch in the sampling flip-flops. This will lead to a biased random numbers with reduced entropy. These issue must be overcome by additional extractor circuits (e.g. Von-Neumann extractor), resulting in additional area and power overhead.
In Chengxin Liu, et al.: “A digital-PLL-based true random number generator,” Research in Microelectronics and Electronics, 2005 PhD, vol.1, no.,pp.113,116 vol.1, 25-28 Jul. 2005, a true random number generator based on a phase locked loop is presented which generates random numbers by means of two identical oscillators, one of which is regulated by phase comparing. With other words, it is proposed to use the clock output signals of two different ring oscillators and combines them by an additional sampling flip-flop. These ring-oscillators are dedicated only for random number generation and provide an area and power overhead. To generate random numbers with good properties (e.g. bias-free) the frequency of the ring oscillators is regulated by extra components (e.g. digital counters). Beside the provided area and power overhead another disadvantage of this approach is that not more than two ring-oscillators can be combined for random number generation.
An efficient generation of true random numbers requires a low resource consumption and high data throughput per area, whereas per area considers the chip area that is needed for processing the true random number generation. Furthermore, low energy consumption per bit with high entropy of the random signal should be required. The main disadvantages of previous solutions are that dedicated circuits (e.g. ring oscillators) are used for entropy generation. The disadvantages of these conventional TRNGs are the extra costs in term of power consumption and area. And some of the proposed circuits require extra calibration circuits to produce bias-free random numbers.
Another important property is the cost-feasibility (production costs).